The present invention relates to a semiconductor device in which a power vertical MOSFET (referred to hereinafter as VDMOS), and another circuit component such as CMOS are formed in a single semiconductor chip.
Recently, there is proposed an integrated circuit device (so-called power IC) in which a power VDMOS used as a switching element for various loads mounted on a vehicle, and other components, such as CMOS, forming a peripheral circuit of the VDMOS are monolithically formed in a single chip.
To facilitate understanding of the present invention, reference is first made to a conventional example shown in FIG. 6. A power IC device of FIG. 6 includes at least one VDMOS 10, and at least one CMOS consisting of a p channel MOSFET (pMOS) 20 and an n channel MOSFET (nMOS) 30. These circuit components are formed on and within a single semiconductor substrate, which consists of a highly doped n.sup.+ bottom layer 1 including a bottom surface of the substrate, and a lightly doped n.sup.- top layer 2 formed on the bottom layer 1 by epitaxial growth or other techniques. The top layer 2 extends from the bottom layer 1 to a top surface of the substrate.
The VDMOS 10 has a p channel region 3 extending into the n.sup.- top layer 2 from the top surface, and an n.sup.+ source region 4 extending into the p channel region 3 from the top surface. In this VDMOS 10, the n.sup.- top layer 2 serves substantially as a drain region. A gate electrode 6 insulated by a gate oxide film 5 is formed above the p channel region 3 so that a channel 3a can be induced in the p channel region 3 between the n.sup.+ source region 4 and the n.sup.- top layer 2 functioning as a drain. There are further provided a PSG insulating layer 7, a topside source electrode 8 and a bottom drain electrode 9.
The pMOS 20 has a p.sup.+ pair of source and drain regions 11 and 12 both formed in the n.sup.- top layer 2, a gate electrode 14 insulated by a gate oxide film 13, a source electrode 15 and a drain electrode 16. The source electrode 15 is connected to the n.sup.- top layer 2 through an n.sup.+ substrate contact region 17.
The nMOS 30 is formed in a p well 18 which is formed in the n.sup.- top layer 2. The nMOS 30 has an n.sup.+ pair of source and drain regions 21 and 22 both formed in the p well 18, a gate electrode 24 insulated by a gate oxide film 23, a source electrode 25 and a drain electrode 26. The source electrode 25 is connected to the p well 18 through a p.sup.+ well contact region 27.
In this power IC, the potential of the n.sup.- top layer 2 is fixed at a supply voltage Vdd applied from the drain electrode 9, so that the VDMOS 10 and the CMOS are electrically separated, and able to act independently from each other. For this reason, the VDMOS 10 is used in a source follower configuration in which a load is connected between a source electrode 8 of the VDMOS 10 and the ground.
The VDMOS is superior as an output device of the power IC because it is driven by voltage, and it is easy to make the withstand voltage high and the on resistance low. On the other hand, the CMOS is well qualified as a logic device of the power IC because the power consumption is low and the noise margin is high. Therefore, the power IC in which the VDMOS and CMOS are integrated with a relatively simple structure, is advantageous in spite of slight restriction due to the necessity of the source follower configuration.
However, such a simple structure of the above mentioned device cannot reliably prevent interference between the VDMOS and CMOS in a dynamic and transient state, so that this conventional device is liable to cause malfunction as illustrated in 7 and 8.
In an example shown in FIG. 8, power ICs are used in drive circuits of a H bridge type for driving an inductive load 28 such as a DC motor. The circuit of FIG. 8 includes power ICs 40a and 40b and MOSFETs 29 and 31.
When, in the drive circuit of FIG. 8, a VDMOS of the power IC 40a and MOSFET 31 are on, a VDMOS of the power IC 40b and MOSFET 29 are off, the load 28 is driven by a current flowing in directions I.sub.1 and I.sub.2. If the MOSFET 31 is then turned off at some instant, a so-called flywheel current continues flowing in a direction I.sub.3 for a while after that instant. This flywheel current I.sub.3 flows into the source electrode of the VDMOS of the power IC 40b, which is shown in FIG. 7. Because of the flywheel current I.sub.3 flowing into the source electrode 8 of the VDMOS 10 shown in FIG. 7, holes (minority carriers) 32 are injected from the p-type channel region 3 of the VDMOS 10 into the n.sup.- layer 2, and these holes 32 reach the p well 18 of the CMOS.
The flywheel current I.sub.3 has a magnitude approximate to the steady state current of the load 28, and the current density reaches a much higher value as compared with external noise applied to a conventional CMOS IC. Therefore, the CMOS in the power IC is brought into latchup by the holes 32 reaching the p well 18 much more easily than a conventional CMOS IC. For this reason, the conventional power IC shown in FIG. 6 is practically unusable without some means for preventing latchup.
FIG. 9 shows another conventional example. The device of FIG. 9 is provided with a p-type guard ring 33 which is formed in the n.sup.- layer between the VDMOS 10 and the CMOS constituted by the pMOS 20 and the nMOS 30. The guard ring 33 reaches the n.sup.+ bottom layer 1, and surrounds the VDMOS 10. The p guard ring 33 is grounded through a guard ring electrode 34.
The guard ring 33 absorbs the holes 32 which are injected from the p channel region 3 and diffuse toward the CMOS in the n.sup.- layer 2, so that these holes flow out to the ground without reaching the CMOS. The n.sup.+ bottom layer 1 below the guard ring 33 has a high impurity concentration and a hole diffusion length shorter than that of the n.sup.- layer 2. Therefore, the number of the holes diffusing through n.sup.+ bottom layer 1 to the CMOS is relatively small. However, especially, in a power IC having VDMOS and CMOS of large current capacities, the number of the holes flowing to the CMOS through the n.sup.+ bottom layer 1 amounts to such a considerable level as to trigger latchup. It is not possible to reduce the possibility of latchup sufficiently by the guard ring alone.